Master Thesis: Online-Junction-Temperature Estimation of Double-Side-Cooled SiC Power-Module

Work description

Due to their low thermal resistance and therefore better Chip utilization, double side cooled (DSC) power-modules gained significant attention in latest applications. Especially the rapidly accelerating trend towards silicon carbide semiconductors (SiC) promotes DSC-technology as total phase current per Die area can be significantly increased, where the raw semiconductor material Silicon Carbide is still expensive.

Even tough DSC-power-modules offer significant advantages in terms of Chip utilization, there are still major drawbacks related to testing the devices inside the power-inverter. Most prominent disadvantage is the lack of an easy to implement option to monitor junction temperature in operation, which is the main influencing factor for power-module degradation and limited lifetime.
 
This is related to the sandwich structure of the thermal stack, where the bare dies (power chips) are arranged between two individual DBC-Substrates. Above mentioned sandwich structure impedes any optical path with direct visibility to the dies.  To overcome this issue TSEP (Temperature-Sensitive-Electrical Parameters) methods are usually adopted, where the thermal state of the device is monitored using one or more temperature dependent electrical parameters.

Scope of this work is the selection modelling and practical application of a suitable TSEP-method in real Inverter application using a DSC-silicon carbide module. Theoretical results should be evaluated by modelling and on a hardware demonstrator which should be designed as part of this work.
 

Your Responsibilities

•    Literature research on available TSEP-methods
•    Modelling and simulation of different TSEP-methods
•    Selection of a suitable method for a hardware build-up
•    Design of a hardware demonstrator with focus on EMI-robustness
•    Build-up of the demonstrator
•    Measurements
•    Documentation
 

Your Qualifications

•    Literature research on available TSEP-methods
•    Modelling and simulation of different TSEP-methods
•    Selection of a suitable method for a hardware build-up
•    Design of a hardware demonstrator with focus on EMI-robustness
•    Build-up of the demonstrator
•    Measurements
•    Documentation
 

Further information

For writing a master thesis you will receive a monthly fee of gross € 700,-- 
Start: by arrangement (duration approx. 6 months)

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Contact person:  
Theresa Rittenschober, Tel.: +43 664 / 783 397 57, LinkedIn / Xing

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